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Learning FPGA Design

A large number of resources exists for learning FPGA design.

Some of them have been collected and aggregated on this page.

An online class was held by tinyVision.ai, and is available freely:

Video format

  • Digi-Key Intro to FPGA Starts with defining FPGA and covers HDLs, programming flow etc. New to FPGAs? Start here!

  • SystemVerilog in 5 minutes Serie of concise and focused descriptions of the SystemVerilog language.

  • VLSI Chaps Discussion and explanation of ASICs, VLISI, but also SystemVerilog.

  • Digital to FPGA 101 design a circuit in digital convert into verilog and run it on an ice40 FPGA (like Upduino_v3.1).

Examples

General tutorials

Specific topic

Wiki

  • VHDL Wiz Terminology Glossary of many concepts.

  • VHDL Wiz Terminology Glossary of many concepts.

  • Hamsterworks wiki Introduction to FPGAs focused on VHDL. The site is offline, but an archive of the content is still available.

  • VerilogGuide Wiki/Book for learning Verilog from the ground up. Uses Quartus and ModelSim-Altera Starter instead of the open source toolchain

  • Chipress Collection of explanations targetted at aspiring ASICs engineers. Many of the topics are related

  • ChipVerify Wiki covering much of Verilog and SystemVerilog syntax.

  • FPGA key Community focused on providing resources to learn FPGAs.

Simulators

  • EDA playground Online IDE and simulator, quickest way to get started without a dev board.

  • Verilator Simulator for Verilog code. Convert the simulation to a C++ code library that exposes signals as C variables.

  • Icarus Verilog Simulator for Verilog code.

  • Digital digital logic circuit simulator based on logisim. Alternative: https://github.com/logisim-evolution/logisim-evolution

  • HDL Bits Interactive (in browser) verilog syntax lessons. initially assumes no prior knowledge of HDLs but quickly ramps up difficulty

Toolchains

  • oss-tabby-cad A complete toolchain based on top of Yosys.

  • Yosys The central tool connecting the languages front-end and back-ends.

  • GHDL Simulator for VHDL code.

  • MixedSim Tool building on top of ngspice for simulating circuits.

  • verilog to routing Open-Source toolchain alternative to YoSys.

  • open FPGA Older toolchain for CPLD.

  • FASM Low-level format aiming to be a de-facto industry standard for FPGA toolchains.

Courses

Other lists

  • F4PGA Link list Another project aiming to collect links.

  • FPGA Design Elements coding style and notes about various building blocks/design principles. Fantastic list of resources/code examples etc

  • HDL Simulators Wikipedia list of simulators for HDLs.

  • sv-tests results Table summarizing support for all SystemVerilog (and Verilog) features support in various tool.. Useful to check compatibility of a toolchain

Books

Organizations

  • Build an FPGA from 7400 series ICs DIY FPGA competition submission and source. https://github.com/arachnid/dfpga

  • Libre-SOC Open source high performance CPU/GPU/VPU on a chip. Focused on high performance open-sourced OpenPOWER architecture

  • F4PGA Umbrella project based on Yosys for synthesis of code toward an HDL.. Good place to first learn about toolchains, but some dead links

Research papers

Games

  • NandGame Browser based puzzle game about logic gates. serves as litmus test to determine familiarity with digital logic. Good for visual learners